Matthias
6cc948eef8
git-svn-id: file:///srv/dev-disk-by-uuid-17e88007-4d0c-45e0-8757-cacfcc458630/repositories/svn/Diplomarbeit@113 9fe90eed-be63-e94b-8204-d34ff4c2ff93
113 lines
3.2 KiB
C
113 lines
3.2 KiB
C
/******************************************************************************
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*
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* $RCSfile: $
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* $Revision: $
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*
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* This module implements the ISRs for the UARTs on the LPC ARMs.
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* Copyright 2004, R O SoftWare
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* No guarantees, warrantees, or promises, implied or otherwise.
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* May be used for hobby or commercial purposes provided copyright
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* notice remains intact.
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*
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* Modified by Martin Thomas for LPC23xx 24xx
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*****************************************************************************/
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#include "app_types.h"
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#include "LPC_REGS.h"
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#include "uart3.h"
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#include "uart3ISR.h"
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#include "armVIC.h"
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extern uint8_t uart3_rx_buffer[UART3_RX_BUFFER_SIZE];
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extern uint16_t uart3_rx_insert_idx, uart3_rx_extract_idx;
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extern uint8_t uart3_tx_buffer[UART3_TX_BUFFER_SIZE];
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extern uint16_t uart3_tx_insert_idx, uart3_tx_extract_idx;
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extern int uart3_tx_running;
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extern int uart3TxFinished(void);
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int uart3ReceivedCount = 0;
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/******************************************************************************
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*
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* Function Name: uart3ISR()
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*
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* Description:
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* This function implements the ISR for UART3.
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* void
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*
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*****************************************************************************/
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void uart3ISR(void)
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{
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uint8_t iid;
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// perform proper ISR entry so thumb-interwork works properly
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ISR_ENTRY();
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// loop until not more interrupt sources
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while (((iid = U3IIR) & UIIR_NO_INT) == 0)
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{
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// identify & process the highest priority interrupt
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switch (iid & UIIR_ID_MASK)
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{
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case UIIR_RLS_INT: // Receive Line Status
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U3LSR; // read LSR to clear
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break;
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case UIIR_CTI_INT: // Character Timeout Indicator
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case UIIR_RDA_INT: // Receive Data Available
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do
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{
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uint16_t temp;
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uart3ReceivedCount++;
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// calc next insert index & store character
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temp = (uart3_rx_insert_idx + 1) % UART3_RX_BUFFER_SIZE;
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uart3_rx_buffer[uart3_rx_insert_idx] = U3RBR;
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// check for more room in queue
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if (temp != uart3_rx_extract_idx)
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uart3_rx_insert_idx = temp; // update insert index
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}
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while (U3LSR & ULSR_RDR);
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break;
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case UIIR_THRE_INT: // Transmit Holding Register Empty
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while (U3LSR & ULSR_THRE)
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{
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// check if more data to send
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if (uart3_tx_insert_idx != uart3_tx_extract_idx)
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{
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U3THR = uart3_tx_buffer[uart3_tx_extract_idx++];
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uart3_tx_extract_idx %= UART3_TX_BUFFER_SIZE;
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}
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else
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{
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// All data is send (acknownledge this to bus driver)
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uart3TxFinished();
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uart3_tx_running = 0; // clear running flag
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break;
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}
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}
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break;
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default: // Unknown
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U3LSR;
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U3RBR;
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break;
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}
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}
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VICVectAddr = 0x00000000; // clear this interrupt from the VIC
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ISR_EXIT(); // recover registers and return
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}
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