diff --git a/C - Cables/4 - Interlock Cable Assembly/3 - Implementation/0 - Altium Project/LIB/MLA-0387-C4.SchLib b/C - Cables/4 - Interlock Cable Assembly/3 - Implementation/0 - Altium Project/LIB/MLA-0387-C4.SchLib
index 2e4107e..79c1f5a 100644
Binary files a/C - Cables/4 - Interlock Cable Assembly/3 - Implementation/0 - Altium Project/LIB/MLA-0387-C4.SchLib and b/C - Cables/4 - Interlock Cable Assembly/3 - Implementation/0 - Altium Project/LIB/MLA-0387-C4.SchLib differ
diff --git a/C - Cables/4 - Interlock Cable Assembly/3 - Implementation/0 - Altium Project/MLA-0387-C4.PrjPCB b/C - Cables/4 - Interlock Cable Assembly/3 - Implementation/0 - Altium Project/MLA-0387-C4.PrjPCB
index 6655d2b..41de692 100644
--- a/C - Cables/4 - Interlock Cable Assembly/3 - Implementation/0 - Altium Project/MLA-0387-C4.PrjPCB	
+++ b/C - Cables/4 - Interlock Cable Assembly/3 - Implementation/0 - Altium Project/MLA-0387-C4.PrjPCB	
@@ -118,8 +118,8 @@ Name=Silk_bottom
 Value=No
 
 [Parameter8]
-Name=MLA
-Value=MLA-0387-C4
+Name=Rev
+Value=PA1
 
 [Parameter9]
 Name=Project_Title
@@ -130,13 +130,13 @@ Name=PCB_Thickness
 Value=1.6 mm
 
 [Parameter11]
-Name=Rev
-Value=PA0
-
-[Parameter12]
 Name=PCB_Dimension
 Value=10 x 10 mm
 
+[Parameter12]
+Name=MLA
+Value=MLA-0387-C4
+
 [Parameter13]
 Name=MK_Drawn
 Value=TLa
@@ -786,6 +786,46 @@ OutputName9=Export IDF
 OutputDocumentPath9=
 OutputVariantName9=
 OutputDefault9=0
+OutputType10=Ansoft Neutral
+OutputName10=Ansoft Neutral (AutoPCB)
+OutputDocumentPath10=
+OutputVariantName10=
+OutputDefault10=0
+OutputType11=HyperLynx
+OutputName11=HyperLynx (AutoPCB)
+OutputDocumentPath11=
+OutputVariantName11=
+OutputDefault11=0
+OutputType12=Orcad SDT Schematic
+OutputName12=Orcad SDT Schematic (AutoSCH)
+OutputDocumentPath12=
+OutputVariantName12=
+OutputDefault12=0
+OutputType13=Orcad v7 Capture Design
+OutputName13=Orcad v7 Capture Design (AutoSCH)
+OutputDocumentPath13=
+OutputVariantName13=
+OutputDefault13=0
+OutputType14=P-CAD ASCII
+OutputName14=P-CAD ASCII (AutoPCB)
+OutputDocumentPath14=
+OutputVariantName14=
+OutputDefault14=0
+OutputType15=P-CAD V16 Schematic Design
+OutputName15=P-CAD V16 Schematic Design (AutoSCH)
+OutputDocumentPath15=
+OutputVariantName15=
+OutputDefault15=0
+OutputType16=Protel PCB 2.8 ASCII
+OutputName16=Protel PCB 2.8 ASCII (AutoPCB)
+OutputDocumentPath16=
+OutputVariantName16=
+OutputDefault16=0
+OutputType17=SiSoft
+OutputName17=SiSoft (AutoPCB)
+OutputDocumentPath17=
+OutputVariantName17=
+OutputDefault17=0
 
 [OutputGroup10]
 Name=PostProcess Outputs
@@ -1055,6 +1095,7 @@ Type110=1
 Type111=1
 Type112=1
 Type113=1
+MultiChannelAlternate=2
 
 [ERC Connection Matrix]
 L1=NNNNNNNNNNNWNNNWW
diff --git a/C - Cables/4 - Interlock Cable Assembly/3 - Implementation/0 - Altium Project/SCH/MLA-0387-C4.SchDoc b/C - Cables/4 - Interlock Cable Assembly/3 - Implementation/0 - Altium Project/SCH/MLA-0387-C4.SchDoc
index 11f1012..774dbce 100644
Binary files a/C - Cables/4 - Interlock Cable Assembly/3 - Implementation/0 - Altium Project/SCH/MLA-0387-C4.SchDoc and b/C - Cables/4 - Interlock Cable Assembly/3 - Implementation/0 - Altium Project/SCH/MLA-0387-C4.SchDoc differ