/******************************************************************************
 *
 * $RCSfile: $
 * $Revision: $
 *
 * This module implements the ISRs for the UARTs on the LPC ARMs.
 * Copyright 2004, R O SoftWare
 * No guarantees, warrantees, or promises, implied or otherwise.
 * May be used for hobby or commercial purposes provided copyright
 * notice remains intact.
 *
 * Modified by Martin Thomas for LPC23xx 24xx
 *****************************************************************************/
#include "app_types.h"
#include "LPC_REGS.h"

#include "uart3.h"
#include "uart3ISR.h"
#include "armVIC.h"

extern uint8_t  uart3_rx_buffer[UART3_RX_BUFFER_SIZE];
extern uint16_t uart3_rx_insert_idx, uart3_rx_extract_idx;
extern uint8_t  uart3_tx_buffer[UART3_TX_BUFFER_SIZE];
extern uint16_t uart3_tx_insert_idx, uart3_tx_extract_idx;
extern int      uart3_tx_running;

extern int uart3TxFinished(void);

int uart3ReceivedCount = 0;

/******************************************************************************
 *
 * Function Name: uart3ISR()
 *
 * Description:
 *    This function implements the ISR for UART3.
 *
 * Calling Sequence: 
 *    void
 *
 * Returns:
 *    void
 *
 *****************************************************************************/
void uart3ISR(void)
{
  uint8_t iid;

  // perform proper ISR entry so thumb-interwork works properly
  ISR_ENTRY();

  // loop until not more interrupt sources
  while (((iid = U3IIR) & UIIR_NO_INT) == 0)
    {
    // identify & process the highest priority interrupt
    switch (iid & UIIR_ID_MASK)
      {
      case UIIR_RLS_INT:                // Receive Line Status
        U3LSR;                          // read LSR to clear
        break;

      case UIIR_CTI_INT:                // Character Timeout Indicator
      case UIIR_RDA_INT:                // Receive Data Available
        do
          {
          uint16_t temp;

          uart3ReceivedCount++;
          
          // calc next insert index & store character
          temp = (uart3_rx_insert_idx + 1) % UART3_RX_BUFFER_SIZE;
          uart3_rx_buffer[uart3_rx_insert_idx] = U3RBR;

          // check for more room in queue
          if (temp != uart3_rx_extract_idx)
            uart3_rx_insert_idx = temp; // update insert index
          }
        while (U3LSR & ULSR_RDR);

        break;

      case UIIR_THRE_INT:               // Transmit Holding Register Empty
        while (U3LSR & ULSR_THRE)
          {
          // check if more data to send
          if (uart3_tx_insert_idx != uart3_tx_extract_idx)
            {
            U3THR = uart3_tx_buffer[uart3_tx_extract_idx++];
            uart3_tx_extract_idx %= UART3_TX_BUFFER_SIZE;
            }
          else
            {
            // All data is send (acknownledge this to bus driver)
            uart3TxFinished();
            uart3_tx_running = 0;       // clear running flag
            break;
            }
          }

        break;

      default:                          // Unknown
        U3LSR;
        U3RBR;
        break;
      }
    }

  VICVectAddr = 0x00000000;             // clear this interrupt from the VIC
  ISR_EXIT();                           // recover registers and return
}